McDATA 3000 manual Fibre Channel End to End CRC

Fibre Channel End to End CRC

On the FCXL2 adapter board, frame transmission and CRC frame data integrity are controlled by separate hardware components. Upon transmission of a Fibre Channel Frame from the buffer memory to an attached Fibre Channel switch, the FCLX2 transmission hardware will generate a CRC value based upon the actual data within the frame. The FCXL2 CRC data integrity hardware will then insert the CRC value that had been previously verified and forwarded by the peer FCXL2 hardware into the frame CRC field. This insures the Frame Level CRC is based upon the frame data that was present on the ingress FCXL2 adapter. Monitoring of Frame Level CRC errors will be done at the attached Fibre Channel switch.

Fibre Channel End to End CRC

End-to-End CRC (Cyclic Redundancy Check) support is automatically enabled for FC/SCSI Tape Pipelining (Device Extension) configurations under the following conditions.

When powering up or resetting the UltraNet Edge 3000, the FCXL2 Fibre Channel driver will determine if each attached Fibre Channel PCI card has hardware installed with CRC support. The ON/OFF status of End-to-End CRC is displayed in the fcxl2 dump crc_stats user interface command.

When an FCP-SCSI I/O with associated data is received, hardware on the FCXL2 Fibre Channel PCI adapter calculates a CRC value on the entire I/O data payload. This CRC value is forwarded along with the I/O and associated data by the FCXL2 Fibre Channel driver to its peer Fibre Channel PCI adapter.

Upon receipt of the FCP-SCSI I/O to output, the peer FCXL2 Fibre Channel PCI adapter will again calculate a CRC value on the outbound data payload. At the completion of the data phase of the I/O, the FCXL2 Fibre Channel driver will compare the output hardware calculated CRC with the CRC value forwarded from its peer. The status phase of the I/O is then based upon the comparison of the locally generated CRC value with the forwarded CRC value. If the values match, good ending status is presented during the status phase of the associated I/O. If the values do not match, bad ending status is presented during the status phase of the associated I/O. Monitoring of End-to-End detected CRC errors may be done by monitoring the counts at fcxl2 dump crc_stats.

Network Design Criteria 3-13

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