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Cisco MGX 8850 Routing Switch Command Reference
Release 2.0, Part Number 78-10467-04 Rev C0, October 2001
Chapter9 Troubleshooting Commands
dspclksrcs
When you configure a new clock source or the current clock source changes du e to any rea son, the
software goes through the process of validating the new, current clock source again. (For example, th e
reasons other than direct user-configuration can be: the previous clock source goes out of lock or a
resync of the clock sources takes place due to a switch-over or a rebuild.) This validation process takes
the current clock source through the following states:
•in locking—wideband t es t
•in locking—narrowband test
•locked
During these states, the node i s al re ad y usi ng t he new cl oc k s ou r ce a s th e s ynch r on iz in g s ou rce.
You might also see these states—in the sequence previously listed—if the current clock source was
momentarily lost because it drifted out of the lockable range for either the frequency or the phase. In
such a case, the software goes through one more roun d of trying to confirm that the current clock source
is lockable before it declares a cl oc k sou r ce to b e u nl oc ka bl e. If the software finds that, even after thi s
repeated attempt, that the cloc k source is not coming back wit hin the lockable range, it declar es the clock
source as unlockable and pro ceeds to use the next clock in the hierarchy (of primary, secondary, internal
oscillator) as the current clock s ource. The exception to this final validat ion scenario occurs if the current
Table9-3 Reasons for Change of Clock State
Reason Meaning
okay The clock source is okay.
unknown reason The clock manager has no information for Reason.
no clock signal Loss of signal (LOS) on the clock source.
frequency too high The frequency has drifted to o high .
frequency too low The frequency has drifted too low
excessive jitter Jitter has exceeded tolerance f o r th is stratum.
missing card or component The active PXM45 has no clock hardware support.
non-existent logical inter face The interface is non-existe nt or n o t f u nc tioning.
interface does not
support clocking The interface does not support clocking.
phase error The clock manager has detected a phase error in the clock.
unlockable The clock manager has attempted to lock the source but found that
the clock signal from this source is unlockable.
out of lock or null The clock circuitry is again trying to lock a source that went out of
locking range. Note: for Reason, out of lock and null are the same.
reset—not a valid state The clock source has been reset.
in locking—wideband test The clock circuitry is in wide bandwidth mode of the locking
process. In this mode, th e circuit tests the integrity of th e source but
with wide latitude for frequency accuracy. If the source passes this
test, the circuit proceeds to the narrowband test.
in locking—narrow-
band test The clock circuitry is in narrow bandwidth locking mode. In this
mode, the circuit stringently tests the integrity of the source.
locked The clock circuitry is locke d to this source.