Command Dictionary | Analyze Drc Violation |
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E9 — The drivers of wire gates must not be capable of driving opposing binary values.
The following lists the Trace rules violation IDs. For a complete description of these violations refer to the “ Scan Chain Trace Rules” section of the
T2 — The netlist contains the blocked gate. The pin data shows the values the tool simulates for all time periods of the shift procedure.
T3 — The netlist contains all the gates in the backtrace cone of the blocked gate. The pin data shows the values the tool simulates for all time periods of the shift procedure.
T4 — The netlist contains all the gates in the backtrace cone of the clock inputs of the blocked gate. The pin data shows the values the tool simulates for all time periods of the shift procedure.
T5 T6 — The netlist contains all the gates in the backtrace cone of the clock inputs of the blocked gate. The pin data shows the values the tool simulates for all time periods of the shift procedure.
T7 — The netlist contains all the gates in the path between the two failing latches. The pin data shows the values the tool simulates for all time periods of the shift procedure.
T11 — A clock input of the memory element closest to the scan chain input must not be on during the shift procedure prior to the time of the force_sci statement.
T16 — When clocks and write control lines are off and pin constraints are set, the gate that connects to the input of a reconvergent pulse generator sink (PGS) gate in the long path must be at the
T17 — Reconvergent pulse generator sink gates cannot connect to any of the following: primary outputs,
Examples
The following example defines the
FastScan and FlexTest Reference Manual, V8.6_4 |
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