FastScan and FlexTest Reference Manual, V8.6_4
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FlexTest Test Pattern File Format Test Pattern File Formats
The -dumpports switch captures detailed port driver data for Verilog ports and
VHDL std_logic ports. The -r switch specifies that signal and port selection
occurs recursively into subregions.
To create LSI extensions of VCD file for Verilog design from Cadence’s Verilog-
XL (using version 2.3 or later), add following command in the verilog test bench:
$dumpports(instance_path_name,”vcd_filename”)
The stimulus in a VCD file must be periodic to be used in the VCD Reader. You
must define all the pin waveforms using Setup Pin Constraints or Add Pin
Constraints commands in FlexTest setup system mode before invoking the VCD
Reader. You may also need to define waveforms for all primary input pins and
strobe times for all primary input and output pins in a separate control file. This
information is used to cycle events. The information provided in the control file
must be consistent with the pin waveforms defined in FlexTest.
The VCD Reader can perform timing checking on the patterns in the VCD file
against the pin waveform specified in the control file. Any value change on a pin
at a time which is not consistent with its offset or pulse width specified in the
control file is dumped in a message file. You can use this information to modify
the original test vector to make it periodic. By default, the VCD Reader doesn’t
perform the timing checking. You can turn this checking on by using the Set
Timing Checking command in the control file.
The converted cycle vectors can be saved in all vector formats that are supported
in FlexTest by using the save pattern command with external option.
The command Set Pattern Source supports the VCD Reader.
Note
ModelSim places a space in the “literal” for a VHDL slice.