Mentor v8.6_4 manual Command Dictionary Write Libraryverification Setup

Command Dictionary Write Library_verification Setup

Examples

The following example lists the contents of an example basename.flexdo file.

set test cycle 3

//defines the waveforms of all clocks and ram/rom read/write control pins;

add pin constraint clk sr0 1 1 1 //clock clk has offstate 0 add pin constraint clk1 sr1 1 1 1 //clock clk1 has offstate 1 add pin constraint set1 sr1 1 1 1 //clock set1 has offstate 1 set contention check on -all

set clock restriction off set hypertrophic limit off set race data x

set z handling external z set system mode atpg

add faults -all run

report statistics

write netlist Top.verilog -verilog -replace write netlist Top.vhdl -vhdl -replace save pattern pat_verilog -verilog -replace save pattern pat_vhdl -vhdl -replace

exit

The following example lists the contents of an example basename.qverilog file.

qhlib work

qvlcom Top.verilog qvlcom pat_verilog

qhsim “$top_module_name”_ctl -do “run -all”

The following example lists the contents of an example basename.qvhdl file.

qhlib work qvhcom Top.vhdl qvhcom pat_vhdl

qhsim “$top_module_name”_ctl -do “run -all”

FastScan and FlexTest Reference Manual, V8.6_4 2-645