Mentor v8.6_4 manual 134

Analyze Drc Violation Command Dictionary

D10 (FastScan Only) — The netlist contains a transparent capture cell that feeds logic requiring both the new and old values. Upon invocation, the tool reports failures as Errors. FastScan models failing source gates as TIEX.

D11 (FastScan Only) — The netlist contains a transparent capture cell that connects to primary output pins. Upon invocation, the tool reports failures as Warnings and does not use the associated primary output pins (expected values are X). If you specify to Ignore D11 violations with the Set Drc Handling command, you can perform “what-if” analysis of a sub-block on the assumption that all its primary output pins will feed scan cells, and so FastScan eventually removes the cause of the D11 (or possibly replaces it with a D10 violation). In this case the reported fault coverage does not consider the effect of reconvergence through transparent capture cells, and so may not always be accurate. When you Ignore this DRC, patterns that you save may be invalid.

The following lists the Extra rules violation IDs. For a complete description of these violations refer to the Extra Rules section of the Design-for-Test: Common Resources Manual.

E2 — There must be no inversion between adjacent scan cells, the scan chain input pin (SCI) and its adjacent scan cell, and the scan chain output pin (SCO) and its adjacent scan cell.

E3 — There must be no inversion between MASTER and SLAVE for any scan cell.

E4 — Tri-state drivers must not have conflicting values when driving the same net during the application of the test procedures.

E5 — When constrained pins are at their constrained states, and PIs and scan cells are at their specified binary states, X states must not be capable of propagating to an observable point.

E6 — When constrained pins are at their constrained states, the inputs of a gate must not have sensitizable connectivity to more than one memory element of a scan cell.

E7 — External bidirectional drivers must be at the high-impedance (Z) state during the application of the test procedure.

E8 — All masters of all scan-cells within a scan chain must use a single shift clock.

2-134 FastScan and FlexTest Reference Manual, V8.6_4