FastScan and FlexTest Reference Manual, V8.6_4
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Analyze Drc Violation Command Dictionary
violations as it encounters them, and you cannot change either the rule
identification number or the ordering of the specific violations.
The design rule violations and their identification literals divide into five
groups: RAM, Clock, Data, Extra, and Trace rules violation IDs.
The following lists the RAM rules violation IDs. For a complete description of
these violations refer to the “RAM Rules” section of the Design-for-Test:
Common Resources Manual.
A1 — When all write control lines are at their off-state, all write, set, and
reset inputs of RAMS must be at their inactive state.
A2 — A defined scan clock must not propagate to a RAM gate, except for
its read lines.
A3 — A write or read control line must not propagate to an address line of a
RAM gate.
A4 — A write or read control line must not propagate to a data line of a
RAM gate.
A5 — A RAM gate must not propagate to another RAM gate.
A6 — All the write inputs of all RAMs and all read inputs of all data_hold
RAMs must be at their off-state during all test procedures, except
test_setup.
A7 — When all read control lines are at their off-state, all read inputs of
RAMs with the read_off attribute set to hold must be at their inactive state.
The following lists the Clock rules violation IDs. For a complete description of
these violations refer to the “Clock Rules” section of the Design-for-Test:
Common Resources Manual.
C1 — The netlist contains the unstable sequential element in addition to the
backtrace cone for each of its clock inputs. The pin data shows the value
that the tool simulates when all the clocks are at their off-states and when
the tool sets all the pin constraints to their constrained values.
C2 — The netlist contains the failing clock pin and the gates in the path
from it to the nearest sequential element (or primary input if there is no
sequential element in the path.) The pin data shows the value that the tool
simulates when the failing clock is set to X, all other clocks are at their off-
states, and when the tool sets all pin constraints to their constrained values.