FastScan and FlexTest Reference Manual, V8.6_4
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Save Patterns Command Dictionary
•-NOPadding (ASCII patterns only)
An optional switch that saves the ASCII patterns with unpadded scan load and
load data. The tool eliminates the extra X values that are due to short scan
chains. This is the default.
You can only use this switch with the -Ascii format type switch.
If you subsequently input unpadded ASCII patterns into the tool, you must use
the Set Pattern Source command with its -Nopadding switch.
•-PAD0 (ASCII patterns only)
An optional switch that saves the ASCII patterns with values of 0 for don’t
care inputs and scan chain inputs of short scan chains.
•-PAD1 (ASCII patterns only)
An optional switch that saves the ASCII patterns with values of 1 for don’t
care inputs and scan chain inputs of short scan chains.
•-Map mapping_file (FastScan only) (LSITDL patterns only)
This is a required switch only in cases where LSITDL pattern files need to be
saved. The mapping_file provides the names of set points and observe points
associated with each memory library cell used in the design. (This file is part
of the LSI ASIC Kit).
Examples
The following example performs an ATPG run and then saves only the first 15
test patterns to a file in the Verilog format, including the timing information
contained in the timing file:
set system mode atpg
add faults -all
run
save patterns file1 -verilog timefile -end 14
The following example illustrates the module name created in the enhanced
Verilog and VHDL outputs when using the -Procfile switch. If the design name is
“MAIN”, and you issue the following Save Patterns command:
save patterns pattern1.pat -procfile -verilog -repl
the module name in the testbench will be “MAIN_pattern1_pat_ctl”.