Report Drc Rules

Command Dictionary

 

 

occurrence number of that violation, and the hyphen between them. For example, you can analyze the second occurrence of the C3 rule by specifying C3-2. The tool assigns the occurrences of the rules violations as it encounters them; you cannot change either the rule identification number or the ordering of the specific violations.

The design rule violations and their identification literals divide into the following five groups: RAM, Clock, Data, Extra, and Trace rules violation IDs.

The following lists the RAM rules violation IDs. For a complete description of these violations refer to the “ RAM Rules” section of the Design-for-Test: Common Resources Manual.

A1 — When all write control lines are at their off-state, all write, set, and reset inputs of RAMS must be at their inactive state.

A2 — A defined scan clock must not propagate to a RAM gate, except for its read lines.

A3 — A write or read control line must not propagate to an address line of a RAM gate.

A4 — A write or read control line must not propagate to a data line of a RAM gate.

A5 — A RAM gate must not propagate to another RAM gate.

A6 — All the write inputs of all RAMs and all read inputs of all data_hold RAMs must be at their off-state during all test procedures, except test_setup.

A7 — When all read control lines are at their off-state, all read inputs of RAMs with the read_off attribute set to hold must be at their inactive state.

A8 (FlexTest Only)— A RAM must be able to turn off its write operation. The default of this handling is WARNING.

The following lists the Clock rules violation IDs. For a complete description of these violations refer to the “ Clock Rules” section of the Design -for-Test: Common Resources Manual.

C1 — The netlist contains the unstable sequential element in addition to the backtrace cone for each of its clock inputs. The pin data shows the value

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FastScan and FlexTest Reference Manual, V8.6_4

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Mentor v8.6_4 manual Report Drc Rules Command Dictionary