Mentor v8.6_4 manual Setup information may include the following

Test Pattern File Formats FlexTest Test Pattern File Format

The setup information may include the following:

TEST_CYCLE_WIDTH = <integer>;

This defines the width of the test cycle that specifies the number of time units in each test cycle for forcing and/or measuring values at specific time units.

DECLARE INPUT BUS “ibus_name” = <ordered list of primary inputs>;

This optional statement groups several primary inputs into one bus name. Each primary input will be enclosed in double quotes and be separated by commas. For bidirectional pins, they will be placed in both the input and output bus.

DECLARE OUTPUT BUS “obus_name” = <ordered list of primary outputs>;

This optional statement groups several primary outputs into one bus name. Each primary output will be enclosed in double quotes and be separated by commas.

If the circuit has scan operation defined, the scan related information will also be described here. The type of information includes clock information, test_setup information, and scan group information.

The clock information is as follows:

CLOCK “clock_name1” = OFF_STATE = <off_state_value>;

END;

CLOCK “clock_name2” = OFF_STATE = <off_state_value>;

END;

....

....

This defines the list of clocks that are contained in the circuit, and used with the scan operation. The clock data will include the clock name enclosed in double quotes, and the off-state value. For edge-triggered scan cells, the off-state is the value that places the initial state of the capturing transition at the clock input of the scan cell. The clock information must be consistent with the Add Clocks command used in the Setup system mode.

FastScan and FlexTest Reference Manual, V8.6_4 4-13