FastScan and FlexTest Reference Manual, V8.6_4
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Write Library_verification Setup Command Dictionary
Write Library_verification Setup
Tools Supported: FlexTest
Scope: All modes
Usage
WRIte LIbrary_verification Setup basename [-Replace]
Description
Generates ATPG library verification setup files.
The Write Library_verification Setup command allows you to generate three
ATPG setup files:
•A FlexTest dofile to generate verification test vectors as well as VERILOG
and VHDL netlist wrappers for the ATPG library (basename.flexdo).
•A verilog QuickHDL dofile to simulate the generated test vectors from
FlexTest with the original verilog library to check the simulation results
will be the same as the results of using ATPG library(basename.qverilog).
•A VHDL QuickHDL dofile to simulate the generated test vectors from
FlexTest with the original vhdl library to check the simulation results will
be the same as the results of using ATPG library(basename.qvhdl).
Arguments
•basename
A required string that specifies the prefix of all dofiles created.
•-Replace
An optional switch that replaces the contents of the file if the basename
already exists.