Mentor v8.6_4 manual Inputs and Outputs

Inputs and Outputs Introduction

∙Contains functionality for handling embedded RAM and ROM.

∙Contains functionality for simulating and generating test pattern sets for BIST circuitry.

FlexTest-specific features include the following:

∙Supports a wide range of DFT structures.

∙Can display a wide variety of useful information—from design and debugging information to statistical reports for the generated test set.

Inputs and Outputs

FastScan and FlexTest utilize the following inputs:

∙Design - The supported netlist formats are EDDM, EDIF, GENIE, Verilog, VHDL, SPICE and TDL.

∙Test Procedure File - This file defines the operation of the scan circuitry in your design. You can generate the file by hand or using the Write ATPG Setup command in DFTAdvisor. For more information on test procedure files, refer to “ Test Procedure Files” in the Scan and ATPG Process Guide.

∙Library - This file contains model descriptions for all library cells used in your design.

∙Fault List - This is an external fault list that you can use as a source of faults for the internal fault list of FlexTest.

∙Test Patterns - This is a set of externally-generated test patterns that you can use as the pattern source for simulation.

1-2 FastScan and FlexTest Reference Manual, V8.6_4