fastscan | Shell Commands |
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∙
A switch that specifies that design_name is a netlist in Verilog format.
∙-VHDL
A switch that specifies that the design_name is a netlist in VHDL format. You must also have a dft.map file present in the same directory as the VHDL netlist. For information on the format of the dft.map file and the supported VHDL constraints, refer to “ Reading VHDL” in the
∙
A switch that specifies that design_name is a netlist in GENIE format.
∙
A switch that specifies that the design_name is a netlist in Spice format.
∙-MODEL cell_name
A switch and string pair that specifies the name of a cell model in the
∙-FLAT
This option allows you to invoke FastScan on a flattened model. The
∙
A switch and string pair that specifies the name of the file containing the library descriptions for all cell models in design_name.
∙
An optional switch that specifies for FastScan to consider pin, instance, and net pathnames case sensitive. The default is
Regardless of the use of this switch, command names are always case insensitive.
FastScan and FlexTest Reference Manual, V8.6_4 |