Set Drc Handling | Command Dictionary |
|
|
Arguments
∙drc_id
A required
The design rule violations and their identification literals are divided into the following five groups: RAM, Clock, Data, Extra, and Trace rules violation IDs.
The following lists the RAM rules violation IDs. For a complete description of these violations refer to the “ RAM Rules” section of the
A1 — When all write control lines are at their
A2 — A defined scan clock must not propagate to a RAM gate, except for its read lines.
A3 — A write or read control line must not propagate to an address line of a RAM gate.
A4 — A write or read control line must not propagate to a data line of a RAM gate.
A5 — A RAM gate must not propagate to another RAM gate.
A6 — All the write inputs of all RAMs and all read inputs of all data_hold RAMs must be at their
A7 — When all read control lines are at their
A8 (FlexTest Only) — A RAM must be able to turn off its write operation. The default of this handling is WARNING.
The following lists the BIST rule violation IDs. FastScan only supports rule B2. For a complete description of all BIST rule violations, refer to the “ BIST Rules”section of the
B2 — Every scan chain input pin must connect to an LFSR.
FastScan and FlexTest Reference Manual, V8.6_4 |