Mentor v8.6_4 manual ∙ drcid

Set Drc Handling Command Dictionary

Arguments

∙drc_id

A required non-repeatable literal that specifies the identification of the exact design rule violations whose message handling you want to change.

The design rule violations and their identification literals are divided into the following five groups: RAM, Clock, Data, Extra, and Trace rules violation IDs.

The following lists the RAM rules violation IDs. For a complete description of these violations refer to the “ RAM Rules” section of the Design-for-Test: Common Resources Manual.

A1 — When all write control lines are at their off-state, all write, set, and reset inputs of RAMS must be at their inactive state.

A2 — A defined scan clock must not propagate to a RAM gate, except for its read lines.

A3 — A write or read control line must not propagate to an address line of a RAM gate.

A4 — A write or read control line must not propagate to a data line of a RAM gate.

A5 — A RAM gate must not propagate to another RAM gate.

A6 — All the write inputs of all RAMs and all read inputs of all data_hold RAMs must be at their off-state during all test procedures, except test_setup.

A7 — When all read control lines are at their off-state, all read inputs of RAMs with the read_off attribute set to hold must be at their inactive state.

A8 (FlexTest Only) — A RAM must be able to turn off its write operation. The default of this handling is WARNING.

The following lists the BIST rule violation IDs. FastScan only supports rule B2. For a complete description of all BIST rule violations, refer to the “ BIST Rules”section of the Design-for-Test: Common Resources Manual.

B2 — Every scan chain input pin must connect to an LFSR.

2-466 FastScan and FlexTest Reference Manual, V8.6_4