Command Dictionary Set Loop Handling
FastScan and FlexTest Reference Manual, V8.6_4 2-525
FlexTest uses a gate duplication technique to reduce the impact of the TIEX and
DELAY gates that it places to break combinational loops. You can use this
command to turn on this feature thereby allowing FlexTest to performing a further
analysis to verify whether the inserted TIEX and DELAY gates are necessary.
For another look at combinational feedback loops, refer to “Feedback Loops” in
the Scan and ATPG Process Guide.
Arguments
•Tiex
A literal that specifies that TIE-X gates are used to break combinational loops.
•Simulation
A literal that specifies for the tool to use a simulation process to stabilize
values in the loop. This option gives more accurate simulation results than
other options. This is the default.
•Delay (FlexTest Only)
A literal that inserts a delay element to break a loop.
•-Duplication ON | OFf
An optional switch and literal pair that specify whether the tool can insert
duplicate gates to reduce the impact of the gates that the tool places to break
combinational loops. The literal choices are as follows:
oON — An optional literal that specifies for the circuit learning process
to generate duplicate gates within any identified feedback paths.
oOFf — An optional literal that specifies for the circuit learning process
to not generate duplicate gates within any identified feedback paths.
This is the default upon invocation.
FlexTest — If this option is selected, FlexTest does no further analysis
to verify whether the inserted TIEX and DELAY gates are necessary.
Because some combinational loops are functionally incapable of
actually behaving as a loop, you can eliminate those unnecessary TIEX
and DELAY gates that FlexTest would have inserted.