Command Dictionary | Set Contention Check |
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FlexTest contention checking is performed for every timeframe so captured data effects are propagated. This is the invocation default behavior.
∙Capture_clock (FastScan Only)
A literal that specifies for the tool to perform contention checking both with and without propagating captured data effects.
If a clock, read control, or write control line connects to a bus, the tool also performs bus contention checking with all clocks off prior to the application of the capture clock. FastScan does not consider any contention patterns for fault simulation and does not place any of these patterns into the internal test pattern set.
∙
An optional switch that specifies for the tool to display a warning message, but continue simulation, if bus contention occurs during simulation. This is the default.
For FastScan — The warning message indicates the number of patterns the
tool rejected in the current simulation pass of 32 patterns and also identifies the bus gate on which the bus contention occurred.
∙
An optional switch that specifies for the tool to display an error message and stop the simulation if bus contention occurs.
You can debug contention errors by using the
Using this option, you can then view the simulated values of all gates in the first bus contention pattern by using the Report Gates command.
For FastScan — The error message indicates the number of patterns the tool rejected in the current simulation pass of 32 patterns and also identifies the bus gate on which the bus contention occurred.
∙
An optional switch that specifies for the tool to perform contention checking of
FastScan and FlexTest Reference Manual, V8.6_4 |