Command Dictionary Set Contention Check
FastScan and FlexTest Reference Manual, V8.6_4 2-457
FlexTest contention checking is performed for every timeframe so captured
data effects are propagated. This is the invocation default behavior.
•Capture_clock (FastScan Only)
A literal that specifies for the tool to perform contention checking both with
and without propagating captured data effects.
If a clock, read control, or write control line connects to a bus, the tool also
performs bus contention checking with all clocks off prior to the application of
the capture clock. FastScan does not consider any contention patterns for fault
simulation and does not place any of these patterns into the internal test pattern
set.
•-Warning
An optional switch that specifies for the tool to display a warning message, but
continue simulation, if bus contention occurs during simulation. This is the
default.
For FastScan — The warning message indicates the number of patterns the
tool rejected in the current simulation pass of 32 patterns and also identifies the
bus gate on which the bus contention occurred.
•-Error
An optional switch that specifies for the tool to display an error message and
stop the simulation if bus contention occurs.
You can debug contention errors by using the -Error switch to stop simulation
at the point of the first contention error.
Using this option, you can then view the simulated values of all gates in the
first bus contention pattern by using the Report Gates command.
For FastScan — The error message indicates the number of patterns the tool
rejected in the current simulation pass of 32 patterns and also identifies the bus
gate on which the bus contention occurred.
•-Bus
An optional switch that specifies for the tool to perform contention checking of
tri-state driver buses. This is the default.
Tri-state logic allows several bus drivers to time-share a bus. However, if the
circuit enables two bus drivers of opposite logic to drive the bus, physical