Add Atpg Constraints | Command Dictionary |
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An optional switch specifying that the tool only need satisfy the ATPG constraints during the ATPG process and not during design rules checking. You can change these constraints during the ATPG process, therefore, Design Rules Checking (DRC) does not check these constraints. This is the default behavior.
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An optional switch specifying that the tool (during all its processes) must always satisfy the ATPG constraint you are defining. You can only add or delete static ATPG constraints when you are in Setup mode, ensuring that the tool uses the static ATPG constraints for all ATPG analyses during design rules checking. DRC checks for any violations of ATPG constraints during the simulation of the test procedures (rule E12).
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An optional switch specifying that the tool suppress checking of specified ATPG constraints after the capture clock. By default, the tool checks ATPG constraints at the same time as bus contention. If, and only if, the tool performs contention checking after the capture clock, the tool also checks ATPG constraints after the capture clock.
In some situations, you may have some ATPG constraints that do not need to be checked after the capture clock, although you may want the tool to check other constraints and bus contention after the capture clock. In this case, you can use the
Examples
The following example creates a
add atpg functions and_b_in and /i$144/q /i$141/q /i$142/q add atpg constraints 0 /i$135/q
add atpg constraints 1 and_b_in
FastScan and FlexTest Reference Manual, V8.6_4 |
