Command Dictionary | Report Gates |
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∙Case 1: No Capture Clock
There will be 1 or 2 values in the last pair of ()s. The first value is the simulation state that results from holding all PIs at their pin constrained value and setting all clocks to X at the end of load/unload.
If any state element has a different binary value than the one it had at the end of simulating test setup, its value will be changed to X, the affect propagated, and the final values saved in the second value between the ()s. See the following examples:
procedure shift = force_sci 0; measure_sco 0; force clk 1 1; force clk 0 2; period 3;
procedure load_unload = force clk 0 0; force rst 0 0; force sen 1 0; apply shift 7 1; period 3;
end;
rep ga clk
///CLK primary_input
//CLK O (0)(0X0)(0)(X)
The first (0) is the simulation of the events in the load_unload procedure prior to the apply shift, (0X0) is the simulation of the shift procedure, (0) is the simulation of the events in the load_unload after the shift, and finally
(X) is the simulation of the clocks at X.
FastScan and FlexTest Reference Manual, V8.6_4 |
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