Mentor v8.6_4 - page 738

FastScan and FlexTest Reference Manual, V8.6_4
4-34
FlexTest Test Pattern File Format Test Pattern File Formats
end
test_vcd test_vcd_inst (.rb(rb), .in2(in2), .cnt1(cnt1), .clk(clk), .buf_in(buf_in),
.ixo(ixo), .out_ff(out_ff), .out1(out1), .buf_out(buf_out));
initial begin
// This is the command used for generating LSI extension of VCD file from Verilog-XL
$dumpports(test_vcd_inst,”lixin_dump”);
_compare_fail = 0;
_pattern_count = 0;
/* The begining of output pattern section */
/* Cycle test block */
/* Pattern 0 */
_pattern_count = 0;
#0; /* 4000 */
_ibus=6’b01101Z;
#2000; /* 6000 */
_ibus=6’b01111Z;
#1000; /* 7000 */
_exp_obus=4’b0Z1Z;
_msk_obus=4’b1111;
-> compare_exp_sim_obus;
/* Pattern 1 */
_pattern_count = 1;
#1000; /* 8000 */
_ibus=6’b10101Z;
#2000; /* 10000 */
_ibus=6’b10111Z;
#1000; /* 11000 */
_exp_obus=4’b1Z1Z;
_msk_obus=4’b1111;
-> compare_exp_sim_obus;
/* Pattern 2 */
_pattern_count = 2;
#1000; /* 12000 */
_ibus=6’b01001Z;
#2000; /* 14000 */
_ibus=6’b01001Z;
#1000; /* 15000 */
_exp_obus=4’b0111;
_msk_obus=4’b1111;