FastScan and FlexTest Reference Manual, V8.6_4
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Set Capture Clock Command Dictionary
In FlexTest, the capture limit must be set at one, the capture clock must have an
R0 or R1 pin constraint, and all other clocks must have a C0, C1, CR0, or CR1 pin
constraint. The period of all pin constraints must be 1.
If you define a capture clock to pass the design rules checker, FlexTest will not
place the chain test (which does not use any capture clock) in any test pattern set.
If you request to save both the cycle and chain test by using the Save Patterns
command, FlexTest will save only the cycle test, and the command displays a
message indicating that FlexTest cannot save the chain test. If you specify to save
only the chain test, FlexTest generates an error message.
If you want a chain test when it is necessary for FlexTest to force a capture clock
for a successful scan test, you can remove the capture clock from the load_unload
procedure in the test procedure file. You must remove the forced capture clock
and then, after the design successfully passes the rules checking, you can store the
chain test in a separate file.
Arguments
•primary_input_pin
A string that specifies the name of the primary input pin that you want to
assign as the capture clock.
•-Atpg
An optional switch that specifies for the tool to use the capture clock for all
scan patterns it creates during the ATPG process and places in the internal
pattern set.
If you are using FastScan and you specify a clock_procedure_name with the
-Atpg switch, then, in the test procedure file, you can apply the clock
procedure to every clock cycle.
Examples
The following example specifies a capture clock:
add clocks 1 clock1
set capture clock clock1
set system mode fault
set random patterns 612
analyze control
report control data