Set Simulation Mode | Command Dictionary |
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oThe test pattern generator identified the fault as combinationally ATPG untestable during the combinational test.
oThe simulation mode is set to Ram_sequential.
oThe fault is connected to an address or write line of an eligible RAM
The test pattern generator then creates a sequential test depending on how the fault propagates to the RAM. The test pattern generator will only try to create a test that satisfies one of the following conditions, and if unsuccessful it will consider the fault to be aborted even if the maximum number of remade decisions has not been exceeded:
oWrite Port Address Lines Faults:
Vector 1 - For the first data line of the fault write port, write 0 into the address where the fault address line is at the fault value and the other address lines are 0 (address A).
Vector 2 - For the first data line of the fault write port, write 1 into the address where the fault address line is at the complements of the fault value and the other address lines are 0.
Vector 3 - From the first data line of the first read port, read 0 from address A.
oRead Port Address Line Faults:
Vector 1 - For the first data line of the first write port, write 0 into the address where the fault address line is at the fault value and the other address lines are 0.
Vector 2 - For the first data line of the first write port, write 1 into the address where the fault address line is at the complement of the fault value and the other address lines are 0 (address A).
Vector 3 - From the first data line of the fault read port, read 1 from address A.
| FastScan and FlexTest Reference Manual, V8.6_4 |
