Mentor v8.6_4 manual Example of the LSI Logic Extended VCD Plus Format Patterns

Models: v8.6_4

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Test Pattern File Formats

FlexTest Test Pattern File Format

 

 

SET PAttern Source Internal {{External filename} [-Ascii -Table -Vcd][-Controlcontrol_filename] [-NOPadding]}

The above usage is for FlexTest only.

Note

Example of the LSI Logic Extended VCD Plus Format Patterns

$date March 2, 1997 10:05:01 $end $version VERILOG-XL 2.3 $end $timescale 1 ns $end

$scope module adder $end $var port 1 <0 carry $var port 4 <1 data $var port 1 <2 test $var port 1 <3 write $upscope $end $enddefinitions $end

#0

pD 6 0 <0 pU 0 6 <1 pD 6 0 <2

pDDDD 6666 0000 <3 #10

pL 6 0 <1 #100

pX 6 0 <2

VCD Reader Control File Commands

Following commands are supported in the control file of the VCD Reader.

1.Add Timeplate timeplate_name period data_sample_time offset [pulse_width]

oThis command adds a timeplate. Timeplates are used to defined the waveforms for primary input pins. All time values in this command must be based upon the timescale that appears in the VCD file (for example, line 3 of “Example of the LSI Logic Extended VCD Plus

FastScan and FlexTest Reference Manual, V8.6_4

4-29

Page 733
Image 733
Mentor v8.6_4 manual Example of the LSI Logic Extended VCD Plus Format Patterns