Command Dictionary Report Drc Rules
FastScan and FlexTest Reference Manual, V8.6_4 2-289
E3 — There must be no inversion between MASTER and SLAVE for any
scan cell.
E4 — Tri-state drivers must not have conflicting values when driving the
same net during the application of the test procedures.
E5 — When constrained pins are at their constrained states, and PIs and
scan cells are at their specified binary states, X states must not be capable of
propagating to an observable point.
E6 — When constrained pins are placed at their constrained states, the
inputs of a gate must not have sensitizable connectivity to more than one
memory element of a scan cell.
E7 — External bidirectional drivers must be at the high-impedance (Z)
state during the application of the test procedure.
E8 — All masters of all scan-cells within a scan chain must use a single
shift clock.
E9 — The drivers of wire gates must not be capable of driving opposing
binary values.
E10 — Performs bus contention mutual-exclusivity checking. Similar to
E4, but does not check for this condition during test procedures.
E11 — A bus must not be able to attain a Z state.
E12 — The test procedures must not violate any ATPG constraints.
E13 — Satisfy both ATPG constraints and bus contention prevention (for
buses that fail rule E10)
The following lists the Trace rules violation IDs. For a complete description of
these violations refer to the “Scan Chain Trace Rules” section of the Design-for-
Test: Common Resources Manual:
T2 — The netlist contains the blocked gate. The pin data shows the values
the tool simulates for all time periods of the shift procedure.
T3 ��� The netlist contains all the gates in the backtrace cone of the blocked
gate. The pin data shows the values the tool simulates for all time periods of
the shift procedure.