Mentor v8.6_4 manual 239

Command Dictionary Load Paths

If the path includes a clock or state element D-input pin, you must include the state element name in the path (or use the -Force switch). Fail to do so and FastScan will not resolve the path and report an error.

∙The last pin for a path must be a valid capture point or a clock input of a scan cell. A valid capture point is a primary output or a data input of a scan cell state element, or it can be a data input of a non-scan state element that satisfies the C1 clock rule.

∙Each pin must have unambiguous fan-in connectivity to the preceding pin, which must not tie to a constant logic value. If the pin fails to have a valid connection with the preceding pin, FastScan generates an error and terminates the Load Paths command. However, if there is ambiguity in the connectivity, FastScan selects a path between the pin and the preceding pin and generates a warning message. You can display the gates in the complete path using the Report Path command.

∙Paths cannot propagate through RAM gates, ROM gates, or transparent latches.

∙Paths cannot have edge ambiguity during any point in the path. An edge that propagates through XOR gates or the select lines of MUX gates can result in either a rising or falling edge at the gate outputs. You can use inversion parity to avoid edge ambiguity. If this check fails, FastScan generates a warning and you can assume that an edge on the pin is not inverted relative to the preceding pin.

∙The condition statements in the path definition file must occur before the first pin statement and before FastScan checks for valid pin names and values. FastScan does not use the conditions to resolve edge or path ambiguities.

For more information on path delay faults and the path definition file, refer to “ Creating a Path Delay Test Set” in the Scan and ATPG Process Guide.

FastScan and FlexTest Reference Manual, V8.6_4 2-239