Mentor v8.6_4 manual ∙ Atpgc

Command Dictionary Set Drc Handling

For more information on using the -Mode option, refer to “ Screening Out False C3 and C4 Violations” in the Design-for-Test: Common Resources Manual.

∙-Interval number

An optional switch and integer pair that you can only use with C3 and C4 clock violations to specify how often you want the tool to display a message during the ATPG analysis of those violations. The number argument indicates multiples of violation occurrences that cause the tool to display a message. The default is 0.

The message includes the number of sequential elements that the tool checked, the number of sequential elements remaining to check, the current number of ATPG passes during the C3 or C4 clock rules checking, and the current CPU time used by the tool for clock rules checking.

The value of the number parameter must be either zero or a positive integer. You can only specify one number value that the tool uses for both the C3 and C4 violations. If you issue multiple Set Drc Handling commands (one for C3 and one for C4) that specify different values for the number argument, the tool uses the last interval value you specified.

∙ATPGC

An optional literal that specifies for the design rules checker to use all the current ATPG constraints when performing the analysis of the C1, C3, C4, C5, C6, E10, and E11 rule violations. You can also use the Add Atpg Constraints -Static command to do the same thing.

∙-Mode {Combinational Sequential}

An optional switch and literal for the tool to use with the E10 rule. The Combinational option is the default. It performs bus contention mutual- exclusivity checking and is limited by the combinational logic boundary.

The Sequential option considers the inputs to a single level of sequential cells behaving as “staging” latches in the enable lines of tri-state drivers. All of the latches found in a back trace must share the same clock. There must also be only a single clocked data port on each cell, and both set and reset inputs must be tied (not pin constrained) to the inactive state. This check ensure that there is no connectivity from the cells in the input cone of the sequential cells and enables of the tri-state devices except through the sequential cells.

FastScan and FlexTest Reference Manual, V8.6_4 2-473