Command Dictionary Set Contention Check
FastScan and FlexTest Reference Manual, V8.6_4 2-459
indicating the number of these aborted faults for each simulation pass. No
attempt is made to change the original pattern.
The -Atpg option results in additional effort by the test pattern generator and
you should use it only when necessary.
•-Verbose (FastScan Only)
An optional switch that reports the first reason for each pattern rejected
(maximum of 32 messages per parallel pattern invocation except on DEC
where maximum is 64).
•-VVerbose (FastScan Only)
An optional switch that reports the every reason for each pattern rejected (there
is no limit to the number of messages per parallel pattern invocation).
•-NOVerbose (FastScan Only)
An optional switch that allows you to turn off the -Verbose or -VVerbose
effects that may have been set previously.
•-Start frame# (FlexTest Only)
An optional switch and integer that specifies the number of timeframes after
initialization, or after each scan loading, when ATPG begins the contention
check. The default is timeframe 0.
Due to sequential initialization, the initial states on a bus may be unknown and
possible contention may be unavoidable. Thus, this switch allows you to begin
the contention checking after design initialization.
Examples
The following example performs contention checking on multiple-port flip-flops
and latches, stops the simulation if any bus contention occurs, and displays an
error message. The message indicates the number of patterns rejected and the bus
gate on which the bus contention occurred:
Note
For large designs, this option may produce thousands of lines of
output for each pattern simulated.