Mentor v8.6_4 - page 532

FastScan and FlexTest Reference Manual, V8.6_4
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Set Iddq Checks Command Dictionary
For FlexTest, the pin constraints of all read control inputs can not be at an on
state at the last timeframe of each test cycle. Otherwise, the tool cannot
perform an IDDQ measurement.
•-WIre
An optional switch specifying that all inputs of a wire gate must be set to the
same value. There should be no contention on wires during IDDQ
measurements because contention can raise the IDDQ current.
•-WEAKHigh
An optional switch specifying that a bus gate must not be at a high state
controlled by a weak value at its input. That is, if a bus gate does not have a
bus_keeper with a zhold1, then the bus cannot have a weakhigh value during
the IDDQ measurement.
•-WEAKLow
An optional switch specifying that a bus gate must not be at a low state
controlled by a weak value at its input. That is, if a bus gate does not have a
bus_keeper with a zhold0, then the bus cannot have a weaklow value during
the IDDQ measurement.
•-VOLTGain
An optional switch specifying that a PMOS transistor must not be at a logic
zero unless a bus_keeper DFT library attribute is available to hold a low state
(zhold0).
•-VOLTLoss
An optional switch specifying that a NMOS transistor must not be at a logic
one unless a bus_keeper DFT library attribute is available to hold a high state
(zhold1).
•-WArning
An optional switch that treats violations of IDDQ checks as warnings. This is
the default.
•-ERror
An optional switch that treats violations of IDDQ checks as errors and stops
the simulation process immediately.