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Set Clock_off Simulation | Command Dictionary |
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Set Clock_off Simulation
Tools: FastScan
Scope: All modes
Usage
SET CLock_off Simulation ON OFf
Description
Enables or disables simulation with the clocks off.
The Set Clock_off Simulation command enables or disables the simulation where all clock primary inputs are at their “off” value, other primary inputs have been forced to values, and state elements are at the values scanned in or resulting from capture in the previous cycle. When simulating this event, FastScan provides the capture data for inputs to leading edge triggered
For more information, refer to “Setting Event Simulation (FastScan Only)” in the Scan and ATPG Process Guide.
Note
Arguments
∙ON
This command is not available for RAM sequential simulations. Since clock sequential ATPG can test the same faults as RAM sequential, this is not a real limitation.
A literal that specifies for the tool to set clock_off simulation ON. The tool reports an error message if you enter the run command while the simulation depth is zero and the Set Clock_off Simulation command is on.
∙OFf
A literal that specifies for the tool to set clock_off simulation OFF. This is the default behavior upon invocation of the tool.
Related Commands
Set Split Capture_cycle
FastScan and FlexTest Reference Manual, V8.6_4 |