Mentor v8.6_4 manual ∙ OFf, ∙ Clockpo FastScan Only

Set Clock Restriction Command Dictionary

Clock_po option. You can accomplish this by setting the clock restriction to Clock_po and then re-running the ATPG.

During the bus contention prevention analysis portion of the ATPG, FastScan turns off any clock pins that the ATPG does not require for fault detection.

For FlexTest — You can prevent race conditions due to multiple active clocks by specifying this behavior. This is the ATPG default behavior upon invocation of FlexTest.

∙OFf

A literal that specifies for the ATPG to create patterns with as many clocks on as it requires to detect faults. Using this option may cause race conditions due to multiple active clocks. You can prevent these race conditions by specifying the On argument.

For FastScan — FastScan concurrently applies any clocks it requires for a given pattern. FastScan displays a message at the end of the ATPG run to indicate the number of patterns that had more than one active clock. When you change the clock restriction to off, FastScan resets the ATPG untestable faults to undetected-uncontrolled.

∙Clock_po (FastScan Only)

A literal that specifies for the ATPG to create patterns independent of the clock restriction. This is the default behavior upon invocation of FastScan.

If the ATPG creates a pattern that requires multiple active clocks but does not detect the fault at the clock PO, the ATPG rejects the pattern and displays a warning message at the end of the run indicating the number of rejected patterns. When you change the clock restriction to off, FastScan resets the ATPG untestable faults to undetected-uncontrolled.

2-452 FastScan and FlexTest Reference Manual, V8.6_4