Mentor v8.6_4 manual ∙ -MODELcellname, ∙ -LIBrary filename

Shell Commands flextest

∙-VERILOG

A switch that specifies that design_name is a netlist in Verilog format.

∙-VHDL

A switch that specifies that the design_name is a netlist in VHDL format. You must also have a dft.map file present in the same directory as the VHDL netlist. For information on the format of the dft.map file and the supported VHDL constraints, refer to “ Reading VHDL” in the Design-for-Test: Common Resources Manual.

∙-GENIE

A switch that specifies that design_name is a netlist in GENIE format.

∙-SPICE

A switch that specifies that the design_name is a netlist in Spice format.

∙-MODELcell_name

A switch and string pair that specifies the name of a cell model in the -LIBrary filename. This is useful for library verification.

∙-LIBrary filename

A switch and string pair that specifies the name of the file containing the library descriptions for all cell models in the design_name.

∙-SENsitive

An optional switch that specifies for FlexTest to consider pin, instance, and net pathnames case sensitive. The default is case-insensitive.

Regardless of the use of this switch, command names are always case insensitive.

∙-LOGfile filename

An optional switch and string pair that specifies the name of the file to which you want FlexTest to write all session information. The default is to display session information to the standard output.

∙-REPlace

An optional switch that overwrites the -Logfile filename if one by the same name already exists.

FastScan and FlexTest Reference Manual, V8.6_4 3-9