FastScan and FlexTest Reference Manual, V8.6_4
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Report Drc Rules Command Dictionary
D3 — The netlist contains all the gates in the backtrace cone of the failing
gate. The pin data shows the values the tool simulates for all time periods of
the master_observe procedure.
D4 — The netlist contains all the gates in the backtrace cone of the failing
gate. The pin data shows the values the tool simulates for all time periods of
the skew_load procedure.
D5 — The netlist contains the disturbed gate, and there is no pin data.
D6 | D7 | D8 — The netlist contains all the gates in the backtrace cone of
the clock inputs of the failing gate. The pin data shows the value that the
tool simulates when all clocks are at their off-states.
D9 — The netlist contains all the gates in the backtrace cone of the clock
inputs of the failing gate. The pin data shows the pattern value the tool
simulated when it encountered the error.
D10 (FastScan Only) — The netlist contains a transparent capture cell that
feeds logic requiring both the new and old values. Upon invocation, the tool
reports failures as Errors. FastScan models failing source gates as TIEX
regardless of the reporting you specify.
D11 (FastScan Only) — The netlist contains a transparent capture cell that
connects to primary output pins. Upon invocation, the tool reports failures
as Warnings and does not use the associated primary output pins (expected
values are X). If you specify to Ignore D11 violations with the Set Drc
Handling command, you can perform “what-if” analysis of a sub-block on
the assumption that all its primary output pins will feed scan cells, and so
FastScan eventually removes the cause of the D11 (or possibly replaces it
with a D10 violation). In this case the reported fault coverage does not
consider the effect of reconvergence through transparent capture cells, and
so may not always be accurate. When you Ignore this DRC, patterns that
you save may be invalid.
The following lists the Extra rules violation IDs. For a complete description of
these violations refer to the “Extra Rules” section of the Design-for-Test:
Common Resources Manual.
E2 — There must be no inversion between adjacent scan cells, the scan
chain input pin (SCI) and its adjacent scan cell, and the scan chain output
pin (SCO) and its adjacent scan cell.