Mentor v8.6_4 manual SET Cycle

Timing Command Dictionary SET CYCLE

SET CYCLE

Scope: Sets timing information

Usage

SET CYCLE integer

Description

Extends the non-scan cycle duration to ensure stability without adding extra timeframes.

FlexTest commonly defines clock pin timing using a test cycle with two timeframes. In this case, the clock goes active sometime within timeframe 2 and goes inactive at the end of timeframe 2. The second clock transition coincides with the input pin forces in the next test cycle, because by default input pin forces occur at time 0 in the first timeframe. This sometimes creates timing violations, such as hold time violations in latch-based designs or setup time violations in multi-edge flip-flop designs.

You can avoid these types of violations by specifying a three-timeframe test cycle. However, as you increase the number of timeframes in a test cycle, fault simulation and ATPG process run-times also increase. The SET CYCLE command provides a solution to this problem. You can use the SET CYCLE command to specify the period of the test cycle, increasing the time of the last timeframe, without having to add more timeframes. This command allows the clock to turn off at the time specified by the last time value of SET FORCE TIME after which no meaningful activity occurs until the start of the new test cycle.

Note that this timing file command is similar to the PERIOD statement that FastScan uses in its TIMEPLATE description.

Arguments

∙integer

The period you wish to set for the test cycle. You must specify a cycle time greater than or equal to the last force time in the cycle, to remain consistent with FlexTest internal simulation.

FastScan and FlexTest Reference Manual, V8.6_4 A-35