Command Dictionary | Set Drc Handling |
|
|
Set Drc Handling
Tools Supported: FastScan and FlexTest
Scope: All modes
Usage
SET DRc Handling drc_id [Error Warning NOTe Ignore] [NOVerbose Verbose] [NOAtpg_analysis Atpg_analysis]
Description
Specifies how the tool globally handles design rule violations.
The Set Drc Handling command specifies the handling of the messages for the scan cell RAM rules checking, Clock rules checking, Data rules checking, Extra rules checking, and Trace rules checking. You can specify that the violation messages for these checks be either error, warning, note, or ignore. If you do not specify error, warning, note, or ignore, then the tool uses either the handling from the last Set Drc Handling command or, if you did not change the handling, the Design Rules Checker‘s invocation default.
Each rules violation has an associated occurrence message and summary message. The tool only displays the occurrence message for either error conditions or if you specify the Verbose option for that rule. The tool displays the rule identification number in all rules violation messages.
The Atpg_analysis option provides test generation analysis when performing rules checking for some clock (C) rules, for some data (D) rules, and for some extra (E) rules. For example, if you specify Atpg_analysis for clock rule C1 and the tool simulates a clock input as X, the rule violation occurs when it is possible for the test generator to create a test pattern while that clock input is on, all defined clocks are off and all constrained pins are at their constrained state.
When you specify Atpg_analysis, the tool requires some additional CPU time and memory to perform the test generation
Note analysis.
FastScan and FlexTest Reference Manual, V8.6_4 |
