Command Dictionary | Report Drc Rules |
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that the tool simulates when all the clocks are at their
C2 — The netlist contains the failing clock pin and the gates in the path from it to the nearest sequential element (or primary input if there is no sequential element in the path.) The pin data shows the value that the tool simulates when the failing clock is set to X, all other clocks are at their off- states, and when the tool sets all pin constrains to their constrained values.
C3 C4 — The netlist contains all gates between the source cell and the failing cell, the failing clock and the failing cell, and the failing clock and the source cell. The pin data shows the clock cone data for the failing clock.
C5/C6 — The netlist contains all gates between the failing clock and the failing cell. The pin data shows the clock cone data for the failing clock.
C7 — The netlist contains all the gates in the backtrace cone of the bad clock input of the failing cell. The pin data shows the constrained values.
C8 C9 — The netlist contains all the gates in the backtrace cone of the failing primary output. The pin data shows the clock cone data for the failing clock.
C10 — For pulse generators and clock procedures in DRC simulation, the netlist contains an element that is clocked more than once.
C11 (FlexTest Only)— A scan shift clock must not have a
C12 (FlexTest Only)— A defined clock must not have a
The following lists the Data rules violation IDs. For a complete description of these violations refer to the “ Scan Cell Data Rules” section of the
D1 — The netlist contains all the gates in the backtrace cone of the clock inputs of the disturbed scan cell. The pin data shows the pattern values the tool simulated when it encountered the error.
D2 — The netlist contains all the gates in the backtrace cone of the failing gate. The pin data shows the values the tool simulated for all time periods of the shift procedure.
FastScan and FlexTest Reference Manual, V8.6_4 |
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