FastScan and FlexTest Reference Manual, V8.6_4
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Set Contention Check Command Dictionary
damage can occur. This switch allows the tool to identify these conditions and
notify you of their existence.
The tool identifies buses which have circuitry that prevent bus contention and
does not check for bus contention problems. This eliminates false bus
contention reporting when multiple inputs to a bus are at X. Bus contention
that occurs on weak buses do not result in an E4 rules checking violation or
pattern rejection during simulation. The tool continues to simulate them as an
X state.
•-Port
An optional switch that specifies for the tool to perform contention checking
for multiple-port flip-flops and latches. The tool identifies and rejects patterns
during which any multiple-port latch or flip-flop has more than one clock, set,
or reset input active (or at X).
•-BIDI_Retain (FastScan Only)
An optional switch that specifies for the tool to reject patterns during
contention checking that cause the direction of IO pins to change following the
capture clock.
•-BIDI_Mask (FastScan Only)
An optional switch that causes the fault simulator to modify the input values of
bidi pins to avoid bus contention after the capture clock of a device pin
changes from input mode to output mode as the clock is applied.
•-ALl
An optional switch that specifies for the tool to perform contention checking
for both tri-state driver buses and multiple-port flip-flops and latches.
•-ATpg
An optional switch that specifies for the tool to force all buses to a non-
contention state, which ensures that the test generator will not create patterns
causing bus contention.
For FastScan — After completing normal test pattern generation for a fault, the
tool forces all buses to a non-contention state. If the tool cannot satisfy this
condition, given the conditions set by the original pattern, the tool aborts the
fault, excludes the pattern from the final test set, and displays a message