Lucent Technologies 555-233-119 Processor Bus Time-out Exception Test,

DEFINITY ECS Release 8.2 Maintenance for R8.2csi 555-233-119 Issue 1
April 2000
Maintenance Objects
3-970PROCR (RISC Processor Circuit Pack TN798)
3
System Technician-Demanded Tests: Descriptions
and Error Codes
Always investigate tests in the order p resented in the table below. By c learing
error codes associated with the
Processor Bus Time-out Exception Test, for
example, you may also clear errors g enerated from other tests in the testing
sequence.
Notes:
a. Refer to ‘‘PR-MEM ( RISC Memo ry)’’ for a description of t hese tests.
Order of Investigation
Short Test
Sequence
Long Test
Sequence D/ND1
1. D = Destructive; ND = Nondestruc tive
Processor Cache Test (#895) X ND
Processor Cache Audit (#896) X X ND
Processor Bus Time-out Exception Test (#82) X X ND
Processor BOOTPROM Checksum Test (#80) X X ND
Processor Write Buffer Test (#900) X X ND
Memory Burst Read Test (#908)(a) X X ND
Read All Memory Test (#85)(a) X ND
Memory Parity Error Detection Test (#87)(a) X X ND
Flash Memory Checksum Test (#86)(a) X ND
Memory Functional Test (#332) (a) (b) X D
MTP Outpulse Relay Test (#102) (c) X X ND
MTP External Modem Present Test (#230) (c) X X ND
MTP Analog Loop Around Test (#103) (c) X X ND
MTP Sanity Handshake Test (#106) (c) X X ND
MTP SAT Loop Around Test (#228) (c) X X ND
MTP Aux Loop Around Test (#229) (c) X X ND
MTP Reset Test (#101) (c) X D
MTP Dual Port Ram Test (#104) (c) X D
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