Lucent Technologies 555-233-119 TDM-CLK (TDM Bus Clock)

DEFINITY ECS Release 8.2 Maintenance for R8.2csi 555-233-119 Issue 1
April 2000
Maintenance Objects
3-1079TDM-CLK (TDM Bus Clock)
3
TDM-CLK (TDM Bus Clock)
NOTE:
Replacing the tone/cloc k circuit pac k requires a special proc edure
described in the documentation for TONE-BD. That section also desc ribes
the LED displays for this board.
The Time Division Multiplex (TDM) Bus Clock resides on the Tone-Clock circuit
pack, providing clocking sig nals both for the TDM Bus and the LAN Bus. The
Tone-Clock circuit pack is a c ritical component in the system and is necessary to
ensure the operation of all port circ uit packs in the system. The TDM buses of the
PPN are synchronized together. The system timing reference c an be derived
internally from the Tone-Clock circuit pack, or from an external (off-board) timing
reference. Currently, the TDM Bus Clock supports sync hronizing the TDM Bus
with interface rates from Digital Signal 1 (DS1) faciliti es as primary or primary and
seconda ry references.
Moreover, the Tone-Clock circuit pack aids in monitoring and selecting
synchronization references. The Tone-Clock circuit pac k, after detecting that the
external source of timing is not valid , will automatically begi n its escalation
procedure, acc ording to the facilities ad ministered.
NOTE:
Switching back to a DS1 source is handled by synchronization
maintenance, once any p roblems with it have been corrected and tested.
However, once synchronization has b een switched to the internal timing
source of the master Tone-Clock circuit pac k,
switch ing back t o a Stra t um 3
Clock must be initiated by a technician
after the external reference has
been repaired.
MO Name (in
Alarm Log)
Alarm
Level Initial Command To Run1
1. P is the cabinet number (1). C is the carrier designation (A, B, or C).
Full Name of MO
TDM-CLK MAJOR test tone-clock PC short TDM Bus Clock
TDM-CLK MINOR test tone-clock PC short TDM Bus Clock
TDM-CLK WARNING release tone-clock PC TDM Bus Clock