DEFINITY ECS Release 8.2 Maintenance for R8.2csi
555-233-119 Issue 1
April 2000
Maintenance Objects
3-1007SYNC (Synchronization)
3
5. Execute the disable synchronization-switch and the enable
synchronization-switch commands. These two commands (when
executed together) switc h the system synchronization reference to
the primary DS1 interface circ uit pack. Check the Error Log and
execute the status synchronization comm and to verify that the
primary DS1 interface circuit pack is still the system
synchronization reference. If the pr imary DS1 interface circuit p ack
is not the system synchronization reference, c ontinue with the
following step.
b. This error indicates that Synchronization Mainten ance has been disab led
via the disable synchronization-switch command. Execute the enable
synchronization-switch command to enable Synchronization
Maintenance reference switching and to resolve this alarm.
c. This error indicates a prob lem with the secondary DS1 reference. It is
cleared when the second ary reference is restored. Refer to note (a) to
resolve this error substituting secondary for primary in the preced ing
resolution steps.
d. This error indicates that the Tone-Clock circuit p ack is providing the timing
source for the system. The primary and s econdary (if administered ) are
not providing a valid timing signal. Investigate e rrors 1 and 257 to resolve
this error.
e. This error indicates excessive switching of system synchronization
references has occurred . When this error occurs, synchronization is
disabled and the Tone-Clock circuit pack (in the master po rt network)
becomes the synchronization referenc e for the system. Execute the
following steps to resolve this error:
1. Check for timing loop s and resolve any loops that exist.
2. Test the active Tone-Clock circuit pack in the master por t network
via the test tone/clock PC long command. Check the Error Log for
TDM-CLK errors and verify that TDM Bus Clock Test #148 passes
successfully. If Test #148 fails with an Error Code 2 through 32, refer
to the TDM-CLK (TDM Bus Clock) Maintenance doc umentation to
resolve the problem. If not, continue wit h the following steps.
3. Replace the primary and secondary (if adm inistered) DS1 Interface
circuit packs.
4. Check for an error logged against the primary or secondary DS1
board. If there is an error, follow the DS1 section to resolve th e
errors. If there is not, enter enable sync, and wait for two to five
minutes for the primary sync sourc e to come on-line.
f. This error indicates that the slave Tone-Clock circuit p ack is experiencing
loss of signal. Refer to note (i) for error resolution steps.
g. The following steps should be executed to resolve error 2049 and 2305:
1. Check for timing loop s, and resolve any loops that exist.