DEFINITY ECS Release 8.2 Maintenance for R8.2csi
555-233-119 Issue 1
April 2000
Maintenance Objects

3-990S-SYN-PT (Speech Synthesis Port)

3
Speech Synthesis SSD Inquiry Test (#167)

This test determines the sanity of the spec ified port’s Speech Synthesis Devic e

(SSD). The on-board microprocessor tests the p ort’s SSD and determines if it is in

a sane (test passes) or insane (test fails) c ondition. Other ports on the Speec h

Synthesis circuit pack c ontinue to function correctl y during this type of failure.

Table 3-437. TEST #166 Speech Synthesis Memory Test
Error
Code
Test
Result Description/ Recommendation
ABORT Could not allocate the necessary system resources to run this test.
1. Retry the command at 1-minute intervals a maximum of 5 times.
1000 ABORT System resources required to run this test are not available. The port may be
busy with a valid call and therefore unavailable for certain tests. You must wait
until the port is idle (yellow LED if off) before retesting.
1. If the port is idle, retry the command at 1-minute intervals a maximum of 5
times.
1019 ABORT Test is already running on a different port, possibly due to b ackground
maintenance activity. Only one of these tests may be active on a circuit pack at
a time.
1. Retry the command at 1-minute intervals a maximum of 5 times.
2000 ABORT Response to the test request was not received within the allowable time period.
2100 ABORT Could not allocate the necessary system resources to run this test.
1. Retry the command at 1-minute intervals a maximum of 5 times.
Any FAIL The computed checksum from the speech vocabulary read-only memory did
not compare correctly with the stored checksum. This type of failure may cause
features using the Speech Synthesis Port’s speech services to malfunction and
result in degradation of synthesized speech quality ranging from insignific ant
to major.
1. Replace the circuit pack.
PASS The computed checksum values were successfully comp ared against the
stored checksum values. User-reported troubles should be investigated using
other tests and verifying other ports on this circuit pack are working c orrectly.
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