DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126 Issue 4
June 1999
Maintenance Object Repair Procedures
9-1343PROCR (RISC Processor Circuit Pack)
9
PROCR (RISC Processor Circuit Pack)
The UN331B Processor circuit pack ex ecutes the system software, includ ing all
call processing, mai ntenance and administration func tions. The Processor circuit
pack is the most critic al component for c orrect system operation.
Full sy stem oper atio n dep end s on n earl y ever y ci rcui t pa ck in the SPE. Howe ver,
the ability to load and r un the maintenance software by the Processor c ircuit
pack depe nds only on correct Mem ory, Processor Bus, Tape-Disk-MSSNET and
SYSAM operation.
There ar e many Proce ssor circ uit p ac k pro blem s (or o ther SPE prob lems ) that will
result in the SPE being unable to load or run software. This condition is indicat ed
by th e mess age "SPE Down" d isp layed on t he ter mina l. In t hese c ase s, ref er to
the SPE DOWN section of this manual for repair procedures.
The Processor circuit pack c ontains an instruction cac he and a data ca che.
These caches provide loc al, high speed memory that is closely coupled with the
processing func tion on the Processor circuit p ack. The local nature of the cac hes
speeds up system op eration by eliminating m any external Memory access es
when reading instructions or d ata. As the Processor runs, it tries to use
information already in the cac he so that time will not be wasted g oing out to
memory. If it does not find the information in the c ache, it reads it from memory
and stores it in the cache for p ossible future use. Over time, most instruc tion or
data accesses are likely to b e satisfied by c urrent information in the cache.
Problems in the cache circ uits may stop the Processor from running or may o nly
result in reduced system p erformance.
The Processor circuit pack c ontains a Burst Read function that transfers multiple
words of instructions from memory with eac h request. This is done to speed up
the transfer of information from the Memory to the Processor, and is especially
helpful for "filling up" the cache in p arallel with internal process ing on Processor
circuit pack. Mos t of the circuitry needed to support this func tion is found on the
MO Name (in
Alarm Log) Alarm
Level Initial Command to
Run1
1. UU is the cabinet number (always 1, not required). With simplex SPE, carrier designation is not
required. With duplicated SPEs, carrier a or b must be specified.
Full Name of MO
PROCR MAJOR2
2. After a spontaneous SPE interchange has occurred, the Alarm Log retains for three hours a
record of any MAJOR ON-BOARD alarm against an SPE component that took place before the
interchange. If a spontaneous interchange has occurred (as indic ated by STBY-SPE error type
103 or the display initcauses screen), and handshake is down, (check with status spe),
replace the alarmed circuit pack on the standb y SPE. If handshake is up, execute a test long
clear of the alarmed circuit pack and follow recommended p rocedures.
test processor UUC l RISC Processor Circuit Pack
PROCR MINOR test processor UUC s RISC Processor Circuit Pack