DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126 Issue 4
June 1999
Maintenance Object Repair Procedures

9-1349PROCR (RISC Processor Circuit Pack)

9
Processor BOOTPROM Checksum Test (#897)

This test computes the chec ksum of the Processor’s bootstrap BOOTPROM and

compares it to a pred etermined value stored within the BOOTPROM. A failure of

this test indicates the BOOTPROM is corrupt.

1339 ABORT The test could not run on the standby Processor circuit pack in the standby
SPE carrier because the standby SPE is unavailable.
1. Refer to the STBY-SPE maintenance documentation for infor mation on why
a standby SPE may be unavailable and what repair actions should be
taken. The screen for the status spe command should indicate that
handshake is down. This may be caused by a variety of reasons such as
the SPE-SELECT switches on the DUPINT circuit packs being set to the
position of the active SPE, a failure of the DUPINT circuit pack, or loss of
power on the standby SPE. The
SPE Select ed
field on the status spe
screen will display
spe a
or
spe b
if bot h SPE-SELECT sw itch es are i n the
a or b positions, respectively.
2000 ABORT Response to the test request was not received within the allowable time period.
If the system is equipped with the High Reliability or Critical Reliability
Configuration and if the Processor circuit pack is on the standby SPE, this
abort code may indicate that the standby SPE is not responding to the
handshake message. If this is the case, the standby SPE maintenance
software may take up to two minutes to indicate that handshake
communication with the standby SPE is down. The ABORT code will then
change to 1339 (standby SPE unavailable).
1. Retry the command at 1-minute intervals, a maximum of 3 times.
2334 ABORT The hardware mail on the standby Duplication Interface board is not ready to
receive messages.
1. Retry the command at 1-minute intervals, a maximum of 5 times.
FAIL The Cache Parity Error bit is set, there may be problems with either the CPU or
the Instruction or Data Cache.
1. Retry the command.
2. If the test continues to fail, run test processor a|b long.
3. If the Processor Cache test (#895) or the Processor Cache Parity Audit
(#896) fails, replace the Proc essor circuit pac k. To replace the Processor
circuit pack, refer to

Repla cing SPE Circ uit Pac ks

in Chapter 5.
PASS The Processor has not detected any parity errors in the Instruction and Data
Caches since the last time this audit was run.
Table 9-529. TEST #896 Processor Cache Parity Audit — Continued
Error
Code Test
Result Description/ Recommendation
Continued on next page