DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126 Issue 4
June 1999
Maintenance Object Repair Procedures
9-1345PROCR (RISC Processor Circuit Pack)
9
Error Log Entries and Test to Clear Values
Notes:
a. This er ror (1 50) in dica tes th at a SPE in terc hang e has o ccu rred a nd th at
the Processor circuit pac k was the cause of the spontaneous interchang e.
1. If other PROCR errors are present, investigate these errors.
2. If no other PROCR errors are present, run the test processor a|b
long clear command and investig ate any test failures.
b. A parity error was detected in the processor’s data c ache or instruction
cac he. In a syst em with dup lica ted SPEs , this error c an b e gen erate d onl y
while the p roces sor is runni ng on the ac tive SPE s ince the so ftwar e
running on the standby p rocessor does not use the Processor d ata and
instruction caches. Therefore, if PROC error 1026 is present for a
proc essor on the stand by SPE, that er ror mu st hav e bee n gene rated some
time i n the p ast w hen the proc esso r was r unnin g as th e act ive SPE.
Execute the test processor long command for a processor eith er on the
active or standby SPE, and if any tests fail, follow the rep air procedures for
those failures. It is unlikely that a parity error will occ ur at the time the
Table 9-527. PROCR Error Log Entries
Error
Type Aux
Data Associated Test Alarm
Level On/Off
Board Test to Clear Value
01
1. Run the Short Test Sequence first. If all tests pass, run the Long Test Sequence. Refer to the
appropriate test description and follow the recommend ed procedures.
0 Any Any Any test processor UUC s r 1
1 BOOTPROM Checksum
Test (#897) MAJOR2
2. If a spontaneous interchange has occurred (as indicated by STBY-SPE error type 103 or the display
init causes screen), and handshake is down, (check with status spe), replac e th e alarmed c i rc uit
pack on the standby SPE. If handshake is up, execute a test long clear of the alarmed circuit pack
and follow recommend ed procedu res.
ON test processor UUC s r 1
150(a) Any None MAJOR†ON test processor UUC l c
257 Parity Checker Test
(#899) MINOR ON test processor UUC s r 2
513 Write Buffer Test (#900) MAJOR†ON test processor UUC s r 1
1025 Cache Audit (#896) MINOR ON test processor UUC s r 2
1026(b) Cache Audit (#896) MAJOR ON test processor UUC s r 2
1281 Cache Test (#895) MAJOR†ON test processor UUC l r 1